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document no. e0250e10 (ver. 1.0) date published march 2002 (k) japan url: http:// www.elpida.com ? elpida memory, inc. 2002 preliminary data sheet 512m bits sdram eds5104abta (128m words 4 bits) eds5108abta (64m words 8 bits) eds5116abta (32m words 16 bits) description the eds5104ab is a 512m bits sdram organized as 33,554,432 words 4 bits 4 banks. the eds5108ab is a 512m bits sdram organized as 16,777,216 words 8 bits 4 banks. the eds5116ab is a 512m bits sdram organized as 8,388,608 words 16 bits 4 banks. all inputs and outputs are referred to the rising edge of the clock input. it is packaged in standard 54- pin plastic tsop (ii). features ? 3.3v power supply ? clock frequency: 166mhz/133mhz (max.) ? lvttl interface ? single pulsed /ras ? 4 banks can operate simultaneously and independently ? burst read/write operation and burst read/single write operation capability ? programmable burst length (bl): 1, 2, 4, 8, full page ? 2 variations of burst sequence ? sequential (bl = 1, 2, 4, 8, full page) ? interleave (bl = 1, 2, 4, 8) ? programmable /cas latency (cl): 2, 3 ? byte control by dqm : dqm (eds5104ab, eds5108ab) : udqm, ldqm (eds5116ab) ? refresh cycles: 8192 refresh cycles/64ms ? 2 variations of refresh ? auto refresh ? self refresh pin configurations /xxx indicates active low si gnal. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 vss nc udqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 vss vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 vdd ldqm /we /cas /ras /cs ba0 ba1 a10 a0 a1 a2 a3 vdd 54-pin tsop (top view) vdd dq0 vddq nc dq1 vssq nc dq2 vddq nc dq3 vssq nc vdd nc /we /cas /ras /cs ba0 ba1 a10 a0 a1 a2 a3 vdd vss dq7 vssq nc dq6 vddq nc dq5 vssq nc dq4 vddq nc vss nc dqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 vss vdd nc vddq nc dq0 vssq nc nc vddq nc dq1 vssq nc vdd nc /we /cas /ras /cs ba0 ba1 a10 a0 a1 a2 a3 vdd vss nc vssq nc dq3 vddq nc nc vssq nc dq2 vddq nc vss nc dqm clk cke a12 a11 a9 a8 a7 a6 a5 a4 vss x 8 x 16 x 4 address input bank select address data-input/output chip select row address strobe column address strobe write enable a0 to a12, ba0, ba1 dq0 to dq15 /cs /ras /cas /we input/output mask clock enable clock input power for internal circuit ground for internal circuit power for dq circuit ground for dq circuit no connection dqm cke clk vdd vss vddq vssq nc
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 2 ordering information part number mask version organization (words bits) internal banks clock frequency mhz (max.) /cas latency package eds5104abta-6b eds5104abta-7a eds5104abta-75* b 128m 4 4 166 133 133 3 2, 3 3 54-pin plastic tsop (ii) EDS5108ABTA-6B eds5108abta-7a eds5108abta-75* 64m 8 166 133 133 3 2, 3 3 eds5116abta-6b eds5116abta-7a eds5116abta-75* 32m 16 166 133 133 3 2, 3 3 note: 100mhz operation at /cas latency = 2. part number :f zfgfu ffvylffvy=v+fu uf ffff.+lf+ ffff.lf fffyqlfyq ffffwlff7h7lf f ffffwlffoi ffffqulffyqqv-7 ffffwlffy77v-=lf7 ffffvlffy77v-7f fffffffffffy..v-= g ffflffzw f fffzlff :fzffvyf.+fwfufwffxffqu
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 3 contents description .................................................................................................................... ................................ 1 features ....................................................................................................................... ................................. 1 pin configurations ............................................................................................................. ............................ 1 ordering information ........................................................................................................... .......................... 2 part number .................................................................................................................... .............................. 2 electrical specifications...................................................................................................... ........................... 4 block diagram .................................................................................................................. ............................. 8 pin function ................................................................................................................... ............................. 13 command operation .............................................................................................................. ..................... 15 simplified state diagram....................................................................................................... ...................... 23 mode register configuration .................................................................................................... .................. 24 power-up sequence.............................................................................................................. ...................... 25 operation of the sdram ......................................................................................................... ................... 27 timing waveforms ............................................................................................................... ....................... 43 package drawing ................................................................................................................ ........................ 49 recommended soldering conditions............................................................................................... ........... 50 revision history ............................................................................................................... ........................... 53
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 4 electrical specifications ? all voltages are referenced to vss (gnd). ? after power up (refer to the power-up sequence). absolute maximum ratings parameter symbol rating unit note voltage on any pin relative to vss vt C0.5 to vdd + 0.5 ( 4.6 (max.)) v supply voltage relative to vss vdd C0.5 to +4.6 v short circuit output current ios 50 ma power dissipation pd 1.0 w operating temperature ta 0 to +70 c storage temperature tstg C55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions (ta = 0 to 70 c) parameter symbol min. max. unit notes supply voltage vdd, vddq 3.0 3.6 v 1 vss, vssq 0 0 v 2 input high voltage vih 2.0 vdd + 0.3 v 3 input low voltage vil C0.3 0.8 v 4 notes: 1. the supply voltage with all vdd and vddq pins must be on the same level. 2. the supply voltage with all vss and vssq pins must be on the same level. 3. vih (max.) = vdd + 2.0 v for pulse width 3n s at vdd. 4. vil (min.) = vss C 2.0 v for pulse width 3ns at vss.
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 5 dc characteristics 1 (ta = 0 to +70 c, vdd, vddq = 3.3v 0.3v, vss, vssq = 0v) parameter max. /cas latency symbol grade 4 8 16 unit test condition notes operating current icc1 -6b,-7a -75 160 140 165 145 175 155 ma burst length = 1 trc = trc (min.) 1, 2, 3 standby current in power down icc2p 3 3 3 ma cke = vil, tck = tck (min.) 6 standby current in power down (input signal stable) icc2ps 2 2 2 ma cke = vil, tck = 7 standby current in non power down icc2n -6b -7a, -75 30 25 30 25 30 25 ma cke, /cs = vih, tck = tck (min.) 4 standby current in non power down (input signal stable) icc2ns 9 9 9 ma cke = vih, tck = , /cs = vih 8 active standby current in power down icc3p 4 4 4 ma cke = vil, tck = tck (min.) 1, 2, 6 active standby current in power down (input signal stable) icc3ps 3 3 3 ma cke = vil, tck = 2, 7 active standby current in non power down icc3n -6b -7a, -75 45 40 45 40 45 40 ma cke, /cs = vih, tck = tck (min.) 1, 2, 4 active standby current in non power down (input signal stable) icc3ns 20 20 20 ma cke = vih, tck = , /cs = vih 2, 8 burst operating current icc4 -6b -7a, -75 160 130 170 140 190 160 ma tck = tck (min.), bl = 4 1, 2, 5 refresh current icc5 -6b,-7a -75 320 280 320 280 320 280 ma trc = trc (min.) 3 self refresh current icc6 4 4 4 ma vih vdd C 0.2v vil 0.2v notes: 1. icc depends on output load condition when the device is selected. icc (max.) is specified at the output open condition. 2. one bank operation. 3. input signals are changed once per one clock. 4. input signals are changed once per two clocks. 5. input signals are changed once per four clocks. 6. after power down mode, clk operating current. 7. after power down mode, no clk operating current. 8. input signals are vih or vil fixed. dc characteristics 2 (ta = 0 to +70 c, vdd, vddq = 3.3v 0.3v, vss, vssq = 0v) parameter symbol min. max. unit test condition notes input leakage current ili C1 1 a 0 vin vdd output leakage current ilo C1.5 1.5 a 0 vout vdd, dq = disable output high voltage voh 2.4 v ioh = C4 ma output low voltage vol 0.4 v iol = 4 ma
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 6 pin capacitance (ta = 25c, vdd, vddq = 3.3v 0.3v) parameter symbol pins min. typ max. unit notes input capacitance ci1 clk 2.5 3.5 pf 1, 2, 4 ci2 address, cke, /cs, /ras, /cas, /we, dqm, 2.5 3.8 pf 1, 2, 4 data input/output capacitance ci/o dq 4 6.5 pf 1, 2, 3, 4 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. measurement condition: f = 1mhz, 1.4v bias, 200mv swing. 3. dqm = vih to disable dout. 4. this parameter is sampled and not 100% tested. ac characteristics (ta = 0 to +70 c, vdd, vddq = 3.3v 0.3v, vss, vssq = 0v) -6b -7a -75 parameter symbol min. max. min. max. min. max. unit notes system clock cycle time tck 6.0 7.5 7.5 ns 1 clk high pulse width tch 2.5 2.5 2.5 ns 1 clk low pulse width tcl 2.5 2.5 2.5 ns 1 access time from clk tac 5.0 5.4 5.4 ns 1, 2 data-out hold time toh 2.5 3.0 3.0 ns 1, 2 clk to data-out low impedance tlz 1 1 1 ns 1, 2, 3 clk to data-out high impedance thz 5.4 5.4 5.4 ns 1, 4 input setup time tsi 1.5 1.5 1.5 ns 1 input hold time thi 0.8 0.8 0.8 ns 1 ref/active to ref/active command period trc 60 60 67.5 ns 1 active to precharge command period tras 42 120000 45 120000 45 120000 ns 1 active command to column command (same bank) trcd 18 15 20 ns 1 precharge to active command period trp 18 15 20 ns 1 write recovery or data-in to precharge lead time tdpl 12 15 15 ns 1 last data into active latency tdal 2clk + 18ns 2clk + 15ns 2clk + 20ns active (a) to active (b) command period trrd 12 15 15 ns 1 transition time (rise and fall) tt 0.5 5 0.5 5 0.5 5 ns refresh period (8192 refresh cycles) tref 64 64 64 ms notes: 1. ac measurement assumes tt = 0.5ns. reference level for timing of input signals is 1.4v. 2. access time is measured at 1.4v. load condition is cl = 50pf. 3. tlz (min.) defines the time at which the outputs achieves the low impedance state. 4. thz (max.) defines the time at which the outputs achieves the high impedance state.
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 7 test conditions ? input and output timing reference levels: 1.4v ? input waveform and output load: see following figures tt 2.4 v 0.4 v 0.8 v 2.0 v input t t i/o cl output load relationship between frequency and minimum latency parameter -6b -7a -75 frequency (mhz) 166 133 tck (ns) symbol 6.0 7.5 7.5 notes active command to column command (same bank) lrcd 3 2 3 1 active command to active command (same bank) lrc 10 8 9 1 active command to precharge command (same bank) lras 7 6 6 1 precharge command to active command (same bank) lrp 3 2 3 1 write recovery or data-in to precharge command (same bank) ldpl 2 2 2 1 active command to active command (different bank) lrrd 2 2 2 1 self refresh exit time lsrex 1 1 1 2 last data in to active command (auto precharge, same bank) ldal 5 4 5 = [ldpl + lrp] self refresh exit to command input lsec 10 8 9 = [lrc] 3 precharge command to high impedance (cl = 2) lhzp 2 2 (cl = 3) lhzp 3 3 3 last data out to active command (auto precharge, same bank) lapr 1 1 1 last data out to precharge (early precharge) (cl = 2) lep C1 C1 (cl = 3) lep C2 C2 C2 column command to column command lccd 1 1 1 write command to data in latency lwcd 0 0 0 dqm to data in ldid 0 0 0 dqm to data out ldod 2 2 2 cke to clk disable lcle 1 1 1 register set to active command lmrd 2 2 2 /cs to command disable lcdd 0 0 0 power down exit to command input lpec 1 1 1 notes: 1. ircd to irrd are recommended value. 2. be valid [desl] or [nop] at next command of self refresh exit. 3. except [desl] and [nop]
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 8 vil/vih clamp this sdram component has vil and vih clamp for clk, cke, /cs, dqm and dq pins. [minimum vil clamp current] vil (v) i (ma) C2 C32 C1.8 C25 C1.6 C19 C1.4 C13 C1.2 C8 C1 C4 C0.9 C2 C0.8 C0.6 C0.6 0 C0.4 0 C0.2 0 0 0 vil (v) i (ma) ?1.5 ?1 ?0.5 ?5 ?15 ?10 ?25 ?20 ?30 0 ?35 ?2 0 minimum vil clamp current
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 9 [minimum vih clamp current] vih (v) i (ma) vdd + 2 10 vdd + 1.8 8 vdd + 1.6 5.5 vdd + 1.4 3.5 vdd + 1.2 1.5 vdd + 1 0.3 vdd + 0.8 0 vdd + 0.6 0 vdd + 0.4 0 vdd + 0.2 0 vdd + 0 0 %p,i ggpspz ggpsp3 ggpspk ggpspzb7 ggpsp3b7 %p,*i o 6 f z k 3z minimum vih clamp current
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 10 iol/ioh characteristics [output low current (iol)] iol iol vout (v) min. (ma) max. (ma) 0 0 0 0.4 27.5 70.2 0.65 41.8 107.5 0.85 51.6 133.8 1 58.0 151.2 1.4 70.7 187.7 1.5 72.9 194.4 1.65 75.4 202.5 1.8 77.0 208.6 1.95 77.6 212.0 3 80.3 219.6 3.45 81.4 222.6 %;[p,*i ;p,i k7z kzz 37z 3zz 7z z z zb7 3 3b7 k kb7 8 8b7 b b output low current (iol)
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 11 [output high current (ioh)] ioh ioh vout (v) min. (ma) max. (ma) 3.45 ? 2.4 3.3 ? 27.3 3 0 ? 74.1 2.6 ? 21.1 ? 129.2 2.4 ? 34.1 ? 153.3 2 ? 58.7 ? 197.0 1.8 ? 67.3 ? 226.2 1.65 ? 73.0 ? 248.0 1.5 ? 77.9 ? 269.7 1.4 ? 80.8 ? 284.3 1 ? 88.6 ? 344.5 0 ? 93.0 ? 502.4 %;p,*i ;,i z ? 100 ? 200 ? 300 ? 500 ? 600 ? 400 0.5 1 1.5 2 2.5 3 min. max. 3.5 0 output high current (ioh)
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 12 block diagram - -fz -f w u ffffffg - - w u ffffffg u - zf-f- f- fgf u z z - -: w v- vw v-w v: uf7 uf= ufy fw -fzfg f- uf. fz
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 13 pin function clk (input pin) clk is the master clock input to this pin. the other input signals are referred at clk rising edge. /cs (input pin) when /cs is low, the command input cycle becomes valid. when /cs is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. /ras, /cas, and /we (input pins) although these pin names are the same as those of conventional drams, they function in a different way. these pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. for details, refer to the command operation section. a0 toa12 (input pins) row address (ax0 to ax12) is determined by a0 to a12 at the bank active command cycle clk rising edge. column address is determined by a0 to a9, a11 or a12 (see address pins table) at the read or write command cycle clk rising edge. and this column address becomes burst access start address. [address pins table] address (a0 to a12) part number row address column address eds5104ab ax0 to ax12 ay0 to ay9, ay11, ay12 eds5108ab ax0 to ax12 ay0 to ay9, ay11 eds5116ab ax0 to ax12 ay0 to ay9 a10 defines the precharge mode. when a10 = high at the precharge command cycle, all banks are precharged. but when a10 = low at the precharge command cycle, only the bank that is selected by ba0 and ba1 (bs) is precharged. for details refer to the command operation section. ba0 and ba1 (input pin) ba0 and ba1 are bank select signal (bs). (see bank select signal table) [bank select signal table] ba0 ba1 bank 0 l l bank 1 h l bank 2 l h bank 3 h h remark: h: vih. l: vil. cke (input pin) this pin determines whether or not the next clk is valid. if cke is high, the next clk rising edge is valid. if cke is low, the next clk rising edge is invalid. this pin is used for power-down mode, clock suspend mode and self refresh mode.
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 14 dqm, udqm and ldqm (input pins) dqm controls input/output buffers. in 32m 16 products, udqm and ldqm control upper byte (dq8 to dq15) and lower byte (dq0 to dq7). read operation: if dqm is high, the output buffer becomes high-z. if the dqm is low, the output buffer becomes low-z. (the latency of dqm during reading is 2 clocks.) write operation: if dqm is high, the previous data is held (the new data is not written). if dqm is low, the data is written. (the latency of dqm during writing is 0 clock.) dq0 todq15 (input/output pins) data is input to and output from these pins (dq0 to dq3; eds5104ab , dq0 to dq7; eds5108ab, dq0 to dq15; eds5116ab). vdd, vss, vddq, vssq (power supply) vdd and vss are power supply pins for internal circuits. vddq and vssq are power supply pins for the output buffers.
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 15 command operation command truth table the sdram recognizes the following commands specified by the /cs, /ras, /cas, /we and address pins. cke function symbol n C 1 n /cs /ras /cas /we ba1,ba0 a10 a0 to a12 device deselect desl h h no operation nop h l h h h burst stop bst h l h h l read read h l h l h v l v read with auto precharge reada h l h l h v h v write writ h l h l l v l v write with auto precharge writa h l h l l v h v bank activate act h l l h h v v v precharge select bank pre h l l h l v l precharge all banks pall h l l h l h mode register set mrs h l l l l l l v remark: h: vih. l: vil. : vih or vil. v: valid address input. device deselect command [desl] when this command is set (/cs is high), the sdram ignore command input at the clock. however, the internal status is held. no operation [nop] this command is not an execution command. however, the internal operations continue. burst stop command [bst] this command can stop the current burst operation. column address strobe and read command [read] this command starts a read operation. in addition, the start address of burst read is determined by the column address (see address pins table in pin function) and the bank select address (ba0, ba1). after the read operation, the output buffer becomes high-z. read with auto-precharge [reada] this command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4 or 8. column address strobe and write command [writ] this command starts a write operation. when the burst write mode is selected, the column address (see address pins table in pin function) and the bank select address (ba0, ba1) become the burst write start address. when the single write mode is selected, data is only written to the location specified by the column address (see address pins table in pin function) and the bank select address (ba0, ba1). write with auto-precharge [writa] this command automatically performs a precharge operation after a burst write with a length of 1, 2, 4 or 8, or after a single write operation.
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 16 row address strobe and bank activate [act] this command activates the bank that is selected by ba0, ba1 and determines the row address (ax0 to ax12). (see bank select signal table) precharge selected bank [pre] this command starts precharge operation for the bank selected by ba0, ba1. (see bank select signal table) [bank select signal table] ba0 ba1 bank 0 l l bank 1 h l bank 2 l h bank 3 h h remark: h: vih. l: vil. precharge all banks [pall] this command starts a precharge operation for all banks. refresh [ref/self] this command starts the refresh operation. there are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. for details, refer to the cke truth table section. mode register set [mrs] the sdram has a mode register that defines how it operates. the mode register is specified by the address pins (a0 to a12, ba0 and ba1) at the mode register set cycle. for details, refer to the mode register configuration. after power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register.
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 17 dqm truth table cke dqm commands symbol n C 1 n udqm ldqm write enable/output enable enb h l write inhibit/output disable mask h h upper byte write enable/output enable enbu h l lower byte write enable/output enable enbl h l upper byte write inhibit/output disable masku h h lower byte write inhibit/output disable maskl h h remark: h: vih. l: vil. : vih or vil write: idid is needed. read: idod is needed. cke truth table cke current state function symbol n C 1 n /cs /ras /cas /we address activating clock suspend mode entry h l any clock suspend mode l l clock suspend clock suspend mode exit l h idle cbr (auto) refresh command ref h h l l l h idle self refresh entry self h l l l l h self refresh self refresh exit l h l h h h l h h idle power down entry h l l h h h h l h power down power down exit l h h l h l h h h remark: h: vih. l: vil. : vih or vil
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 18 function truth table the following table shows the operations that are performed when each command is issued in each mode of the sdram. the following table assumes that cke is high. current state /cs /ras /cas /we address command operation precharge h desl enter idle after trp l h h h nop enter idle after trp l h h l bst illegal l h l h ba, ca, a10 read/reada illegal* 3 l h l l ba, ca, a10 writ/writa illegal* 3 l l h h ba, ra act illegal* 3 l l h l ba, a10 pre, pall nop* 5 l l l h ref, self illegal l l l l mode mrs illegal idle h desl nop l h h h nop nop l h h l bst illegal l h l h ba, ca, a10 read/reada illegal* 4 l h l l ba, ca, a10 writ/writa illegal* 4 l l h h ba, ra act bank and row active l l h l ba, a10 pre, pall nop l l l h ref, self refresh l l l l mode mrs mode register set* 8 row active h desl nop l h h h nop nop l h h l bst illegal l h l h ba, ca, a10 read/reada begin read* 6 l h l l ba, ca, a10 writ/writa begin write* 6 l l h h ba, ra act other bank active illegal on same bank* 2 l l h l ba, a10 pre, pall precharge* 7 l l l h ref, self illegal l l l l mode mrs illegal read h desl continue burst to end l h h h nop continue burst to end l h h l bst burst stop l h l h ba, ca, a10 read/reada continue burst read to /cas latency and new read l h l l ba, ca, a10 writ/writa term burst read/start write l l h h ba, ra act other bank active illegal on same bank* 2 l l h l ba, a10 pre, pall term burst read and precharge l l l h ref, self illegal l l l l mode mrs illegal
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 19 current state /cs /ras /cas /we address command operation read with auto- precharge h desl continue burst to end and precharge l h h h nop continue burst to end and precharge l h h l bst illegal l h l h ba, ca, a10 read/reada illegal* 3 l h l l ba, ca, a10 writ/writa illegal* 3 l l h h ba, ra act other bank active illegal on same bank* 2 l l h l ba, a10 pre, pall illegal* 3 l l l h ref, self illegal l l l l mode mrs illegal write h desl continue burst to end l h h h nop continue burst to end l h h l bst burst stop l h l h ba, ca, a10 read/reada term burst and new read l h l l ba, ca, a10 writ/writa term burst and new write l l h h ba, ra act other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall term burst write and precharge* 1 l l l h ref, self illegal l l l l mode mrs illegal write with auto- precharge h desl continue burst to end and precharge l h h h nop continue burst to end and precharge l h h l bst illegal l h l h ba, ca, a10 read/reada illegal* 3 l h l l ba, ca, a10 writ/writa illegal* 3 l l h h ba, ra act other bank active illegal on same bank* 3 l l h l ba, a10 pre, pall illegal* 3 l l l h ref, self illegal l l l l mode mrs illegal refresh (auto-refresh) h desl enter idle after trc l h h h nop enter idle after trc l h h l bst illegal l h l h ba, ca, a10 read/reada illegal* 4 l h l l ba, ca, a10 writ/writa illegal* 4 l l h h ba, ra act illegal* 4 l l h l ba, a10 pre, pall illegal* 4 l l l h ref, self illegal l l l l mode mrs illegal
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 20 current state /cs /ras /cas /we address command operation mode register set h desl nop l h h h nop nop l h h l bst illegal l h l h ba, ca, a10 read/reada illegal* 4 l h l l ba, ca, a10 writ/writa illegal* 4 l l h h ba, ra act bank and row active* 9 l l h l ba, a10 pre, pall nop l l l h ref, self refresh* 9 l l l l mode mrs mode register set* 8 remark: h: vih. l: vil. : vih or vil notes: 1. an interval of tdpl is required between the final valid data input and the precharge command. 2. if trrd is not satisfied, this operation is illegal. 3. illegal for same bank, except for another bank. 4. illegal for all banks. 5. nop for same bank, except for another bank. 6. illegal if trcd is not satisfied. 7. illegal if tras is not satisfied. 8. mrs command must be issued after dout finished, in case of dout remaining. 9. illegal if lmrd is not satisfied.
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 21 command truth table for cke cke current state n C 1 n /cs /ras /cas /we address operation notes self refresh h invalid, clk (n C 1) would exit self refresh l h h self refresh recovery l h l h h self refresh recovery l h l h l illegal l h l l illegal l l continue self refresh self refresh recovery h h h idle after t rc h h l h h idle after t rc h h l h l illegal h h l l illegal h l h illegal h l l h h illegal h l l h l illegal h l l l illegal power down h invalid, clk (n C 1) would exit power down l h h exit power down l h l h h h exit power down l l continue power down mode all banks idle h h h refer to operations in function truth table h h l h refer to operations in function truth table h h l l h refer to operations in function truth table h h l l l h cbr (auto) refresh h h l l l l opcode refer to operations in function truth table h l h begin power down next cycle h l l h refer to operations in function truth table h l l l h refer to operations in function truth table h l l l l h self refresh 1 h l l l l l opcode refer to operations in function truth table l h exit power down next cycle l l power down 1 row active h refer to operations in function truth table l clock suspend 1 any state other than h h refer to operations in function truth table listed above h l begin clock suspend next cycle 2 l h exit clock suspend next cycle l l maintain clock suspend remark: h: vih. l: vil. : vih or vil notes: 1. self refresh can be entered only from the all banks idle state. power down can be entered only from all banks idle. clock suspend can be entered only from following states, row active, read, read with auto- precharge, write and write with auto precharge. 2. must be legal command as defined in function truth table.
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 22 clock suspend mode entry the sdram enters clock suspend mode from active mode by setting cke to low. if command is input in the clock suspend mode entry cycle, the command is valid. the clock suspend mode changes depending on the current status (1 clock before) as shown below. active clock suspend this suspend mode ignores inputs after the next clock by internally maintaining the bank active status. read suspend and read with auto-precharge suspend the data being output is held (and continues to be output). write suspend and writ with auto-precharge suspend in this mode, external signals are not accepted. however, the internal state is held. clock suspend during clock suspend mode, keep the cke to low. clock suspend mode exit the sdram exits from clock suspend mode by setting cke to high during the clock suspend state. idle in this state, all banks are not selected, and completed precharge operation. auto-refresh command [ref] when this command is input from the idle state, the sdram starts auto-refresh operation. (the auto-refresh is the same as the cbr refresh of conventional drams.) during the auto-refresh operation, refresh address and bank select address are generated inside the sdram. for every auto-refresh cycle, the internal address counter is updated. accordingly, 8192 times are required to refresh the entire memory. before executing the auto-refresh command, all the banks must be in the idle state. in addition, since the precharge for all banks is automatically performed after auto-refresh, no precharge command is required after auto-refresh. self-refresh entry [self] when this command is input during the idle state, the sdram starts self-refresh operation. after the execution of this command, self-refresh continues while cke is low. since self-refresh is performed internally and automatically, external refresh operations are unnecessary. power down mode entry when this command is executed during the idle state, the sdram enters power down mode. in power down mode, power consumption is suppressed by cutting off the initial input circuit. self-refresh exit when this command is executed during self-refresh mode, the sdram can exit from self-refresh mode. after exiting from self-refresh mode, the sdram enters the idle state. power down exit when this command is executed at the power down mode, the sdram can exit from power down mode. after exiting from power down mode, the sdram enters the idle state.
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 23 simplified state diagram :-w: ff: :z fff:wz :z fff w-: z: ffz: : fz fffw :g: ffff:g :g: ffffz: :: fffff: : ffff :w ff:w :z :wzw fff:wzw f:z w-: -- :z f: f: :g: -: -: w-: : :wz : fw :wz fw : w:z -: -: -: -: -: -: -: -: -: -: :-w: w :wz : : w :wz :wz fw : fw :-w: :-w: :-w: u u my :wz : wfffffh ffffh lffyhffwffxflffffff ffffffffffffffffffz:fh
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 24 mode register configuration the mode register is set by the input to the address pins (a0 to a12, ba0 and ba1) during mode register set cycles. the mode register consists of five sections, each of which is assigned to address pins. ba1, ba0, a8, a9, a10, a11, a12: (opcode): the sdram has two types of write modes. one is the burst write mode, and the other is the single write mode. these bits specify write mode. burst read and burst write: burst write is performed for the specified burst length starting from the column address specified in the write cycle. burst read and single write: data is only written to the column address specified during the write cycle, regardless of the burst length. a7: keep this bit low at the mode register set cycle. if this pin is high, the vender test mode is set. a6, a5, a4: (lmode): these pins specify the /cas latency. a3: (bt): a burst type is specified. a2, a1, a0: (bl): these pins specify the burst length. *k *3 *z fp zz z 3 zz 3 k z3 z 6 z3 3 o 33 3 fvz fv3 3z z " 33 z " +bb 3 k 6 o " " " *8 z 3 % fp *f *7 *6 w*p zz z " zz 3 " z3 z k z3 3 8 3 " *c *o *- *f *7 *6 *8 *k *3 *z ;w;gC z [];gC f f[ *c z z" p *o z 3 fpppp 3 fpppp z 3" 3 3z 3 " " +bbqpp+p "pp"p,i qpzpp3 *33 *3z *3z *33 zz *3k f*z f*3 f*3 f*z z z *3k z mode register set timing
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 25 *k *3 *z *,i zz z zz 3 z3 z z3 3 33 3 % 3z z 33 z 3z 3 p*b z4 34 k4 84 64 74 f4 -4 34 k4 84 64 74 f4 -4 k4 84 64 74 f4 -4 84 64 74 f4 -4 64 74 f4 -4 74 f4 -4 f4 -4 -4 z4 z4 34 z4 34 k4 z4 34 k4 84 z4 34 k4 84 64 z4 34 k4 84 64 74 z4 34 k4 84 64 74 f4 z4 34 k4 84 64 74 f4 -4 34 z4 84 k4 74 64 -4 k4 84 z4 34 f4 -4 84 k4 34 z4 -4 64 74 f4 -4 74 64 -4 f4 -4 -4 f4 64 74 f4 74 64 z4 34 k4 84 f4 34 z4 84 k4 64 74 k4 84 z4 34 f4 74 64 84 k4 34 z4 fppvpo *3 *z *,i zz z3 3z 33 % p*b z4 34 k4 84 34 k4 84 z4 k4 84 z4 34 84 z4 34 k4 z4 34 k4 84 34 z4 84 k4 k4 84 z4 34 84 k4 34 z4 fppvp6 *z *,i z 3 % p*b z4 34 34 z4 z4 34 34 z4 fppvpk burst sequence full page burst is available only for sequential addressing. the addressing sequence is started from the column address that is asserted by read/write command. and the address is increased one by one. it is back to the address 0 when the address reaches at the end of address 4,095 (for 128m 4 device), 2,047 (for 64m 8 device) and 1,023 (for 32m 16 device). full page never stops the burst read/write.
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 26 power-up sequence power-up sequence the sdram should be goes on the following sequence with power up. the clk, cke, /cs, dqm and dq pins keep low till power stabilizes. the clk pin is stabilized within 100 s after power stabilizes before the following initialization sequence. the cke and dqm is driven to high between power stabilizes and the initialization sequence. this sdram has vdd clamp diodes for clk, cke, /cs dqm and dq pins. if these pins go high before power up, the large current flows from these pins to vdd through the diodes. initialization sequence when 200 s or more has past after the above power-up sequence, all banks must be precharged using the precharge command (pall). after trp delay, set 8 or more auto refresh commands (ref). set the mode register set command (mrs) to initialize the mode register. we recommend that by keeping dqm and cke to high, the output buffer becomes high-z during initialization sequence, to avoid dq bus contention on memory system formed with a number of device. gg4pgg pp %p 3zzp power-up sequence and initialization sequence
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 27 operation of the sdram read/write operations bank active before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (act) command. an interval of t rcd is required between the bank active command input and the following read/write command input. read operation a read operation starts when a read command is input. output buffer becomes low-z in the (/cas latency - 1) cycle after read command set. the sdram can perform a burst read operation. the burst length can be set to 1, 2, 4 and 8. the start address for a burst read is specified by the column address and the bank select address at the read command set cycle. in a read operation, data output starts after the number of clocks specified by the /cas latency. the /cas latency can be set to 2 or 3. when the burst length is 1, 2, 4 and 8 the dout buffer automatically becomes high-z at the next clock after the successive burst-length data has been output. the /cas latency and burst length must be specified at the mode register. "C*g w[x w g *w " w * w[pvpk w[pvp8 pz p3 pk p8 pz p3 pk p8 "wg w[pvpgw*p fp[pvp6 /cas latency "C*g w[x w g *w " w pz pf p- * pz p3 p6 p7 pz p3 pk p8 f[pvp3 pz p3 pk p8 f[pvpk f[pvp6 f[pvpo "wg f[pqpfp[ gw*p[pvpk burst length
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 28 write operation burst write or single write mode is selected by the opcode of the mode register. 1. burst write: a burst write operation is enabled by setting opcode (a9, a8) to (0, 0). a burst write starts in the same clock as a write command set. (the latency of data input is 0 clock.) the burst length can be set to 1, 2, 4 and 8, like burst read operations. the write start address is specified by the column address and the bank select address at the write command set cycle. "% w[x w g *w " w pz pf p- * p3 p6 p7 p8 f[pvp3 f[pvpk f[pvp6 f[pvpo "wg pz pz pz p3 p3 pk pk p8 w[pvpk4p8 burst write 2. single write: a single write operation is enabled by setting opcode (a9, a8) to (1, 0). in a single write operation, data is only written to the column address and the bank select address specified by the write command set cycle without regard to the burst length setting. (the latency of data input is 0 clock). "% w[x w g *w " w pz * "wg single write
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 29 auto precharge read with auto-precharge in this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. the command executed for the same bank after the execution of this command must be the bank active (act) command. in addition, an interval defined by lapr is required before execution of the next command. [clock cycle time] /cas latency precharge start cycle 3 2 cycle before the final data is output 2 1 cycle before the final data is output w[x *" "* *" w[vkppw w[v8ppw g g yqpp%pappppppprppppprbpp *pppp"*p,"*ipppppp,*wipppppprppppprbpp *w "C*g* *w 8 k 3 z "* *w "C*g* *w 8 k 3 z burst read (bl = 4) write with auto-precharge in this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. the command executed for the same bank after the execution of this command must be the bank active (act) command. in addition, an interval of ldal is required between the final valid data input and input of next command. w[x w g g*[ % "* *w "%* z 3 k 8 *w yqpp%pappppppprppppprb pppp"*p,"*ipppppp,*wipp ppprppppprb burst write (bl = 4)
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 30 w[x w g g*[ %"* *w "%* *w yqpp%pappppppprppppprb pppp"*p,"*ipppppp,*wipp ppprppppprb single write
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 31 burst stop command during a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus goes to high-z after the /cas latency from the burst stop command. w[x w g ,w[pvpki g ,w[pvp8i "C*g f a a burst stop at read during a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes to high-z at the same clock with the burst stop command. w[x w g f "%C a burst stop at write
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 32 command intervals read command to read command interval 1. same bank, same row address: when another read command is executed at the same row address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 clock. even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. w[x w g pf8 * pf3 pfk f *w " wp* "C*g "C*g wpf p*z pfz fz * wpv* " wpvf " wpv* g wpvf g w[pvp8 f[pvp6 fpz read to read command interval (same row address in same bank) 2. same bank, different row address: when the row address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank active command. 3. different bank: when the bank changes, the second read can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. w[x w g pf8 * pf3 pfk f *w "pz "p3 *w "C*g wp* p*z pfz fz * f8 * fz " f8 " "C*g wpf fz g f8 g w[pvp8 f[pvp6 read to read command interval (different bank)
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 33 write command to write command interval 1. same bank, same row address: when another write command is executed at the same row address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 clock. in the case of burst writes, the second write command has priority. w[x w g pf8 * pf3 pfk f *w " wp* "% "% wpf p*z pfz fz * wpv* wpvf fpp] f[pvp6 fpz write to write command interval (same row address in same bank) 2. same bank, different row address: when the row address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank active command. 3. different bank: when the bank changes, the second write can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. in the case of burst write, the second write command has priority. w[x w g pf8 * pf3 pfk f *w "pz "p3 *w "% wp* p*z pfz fz * f8 * fz f8 "% wpf fpp] f[pvp6 write to write command interval (different bank)
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 34 read command to write command interval 1. same bank, same row address: when the write command is executed at the same row address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 clock. however, dqm must be set high so that the output buffer becomes high-z before data input. w[x w gp,i pfk pf8 "C*g "% pfz pf3 a gp,i w[vk w[v8 g] f[pvp6 fp read to write command interval (1) - - z :wz -[= -[7 z =f read to write command interval (2) 2. same bank, different row address: when the row address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank active command. 3. different bank: when the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank active state. however, dqm must be set high so that the output buffer becomes high-z before data input.
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 35 write command to read command interval: 1. same bank, same row address: when the read command is executed at the same row address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 clock. however, in the case of a burst write, data will continue to be written until one clock before the read command is executed. w[x w gp,i "% "C*g p*z pf3 pfk pf8 pfz gp,i wpvp* wpvpf " wpvpf g gw*p[ g] fpp] w[pvpk f[pvp6 fpz write to read command interval (1) w[x w gp,i "% "C*g p*z pf3 pfk pf8 pfz gp,i wpvp* wpvpf " wpvpf g gw*p[ p*3 g] fpp] w[pvpk f[pvp6 fpz write to read command interval (2) 2. same bank, different row address: when the row address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank active command. 3. different bank: when the bank changes, the read command can be performed after an interval of no less than 1 clock, provided that the other bank is in the bank active state. however, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address).
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 36 read with auto precharge to read command interval 1. different bank: when some banks are in the active state, the second read command (another bank) is executed. even when the first read with auto-precharge is a burst read that is not yet finished, the data read by the second command is valid. the internal auto-precharge of one bank starts at the next clock of the second command. w[x w f g "C*g* "C*g p*z p*3 pfz pf3 w[vp8 f[pvp6 z "p* 8 " yqp%pappppppprppppppprb read with auto precharge to read command interval (different bank) 2. same bank: the consecutive read command (the same bank) is illegal. write with auto precharge to write command interval 1. different bank: when some banks are in the active state, the second write command (another bank) is executed. in the case of burst writes, the second write command has priority. the internal auto-precharge of one bank starts 2 clocks later from the second command. w[x w f g "%* "% pf3 pfk pf8 p*z p*3 pfz f[vp6 z p* 8 yqp%pappppppprppppppprb write with auto precharge to write command interval (different bank) 2. same bank: the consecutive write command (the same bank) is illegal.
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 37 read with auto precharge to write command interval 1. different bank: when some banks are in the active state, the second write command (another bank) is executed. however, dqm must be set high so that the output buffer becomes high-z before data input. the internal auto- precharge of one bank starts at the next clock of the second command. w[x w f gp,i gp,i w[pvpk w[pvp8 "C*g* "% pfz pf3 pfk pf8 f[pvp6 z "* 8 yqp%pappppppprppppppprb g] a read with auto precharge to write command interval (different bank) 2. same bank: the consecutive write command from read with auto precharge (the same bank) is illegal. it is necessary to separate the two commands with a bank active command. write with auto precharge to read command interval 1. different bank: when some banks are in the active state, the second read command (another bank) is executed. however, in case of a burst write, data will continue to be written until one clock before the read command is executed. the internal auto-precharge of one bank starts at 2 clocks later from the second command. w[x w f gp,i gp,i "%* "C*g pfz pf3 pfk pf8 w[pvp8 f[pvp6 z * 8 " yqp%pappppppprppppppprb g] p*z write with auto precharge to read command interval (different bank) 2. same bank: the consecutive read command from write with auto precharge (the same bank) is illegal. it is necessary to separate the two commands with a bank active command.
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 38 read command to precharge command interval (same bank) when the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. however, since the output buffer then becomes high-z after the clocks defined by lhzp, there is a case of interruption to burst read data output will be interrupted, if the precharge command is input during burst read. to read all data by burst read, the clocks defined by lep must be assured as an interval from the final data output to precharge command execution. w[x w g "C*g "Cg*[[ p*z p*3 p*k p*8 w[vk Cpvpa3p read to precharge command interval (same bank): to output all data (cl = 2, bl = 4) w[x w g "C*g "Cg*[[ p*z p*3 p*k p*8 w[v8 Cpvpakp read to precharge command interval (same bank): to output all data (cl = 3, bl = 4) w[x w g "C*g "Cg*[[ p*z a vpk read to precharge command interval (same bank): to stop output data (cl = 2, bl = 1, 2, 4, 8) w[x w g "C*g "Cg*[[ p*z v8 a read to precharge command interval (same bank): to stop output data (cl = 3, bl = 1, 2, 4, 8)
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 39 write command to precharge command interval (same bank) when the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 clock. however, if the burst write operation is unfinished, the input data must be masked by means of dqm for assurance of the clock defined by tdpl. w[x w g "% "Cg*[[ g[ g] w[x p*z p*3 w g "% "Cg*[[ g] g[ write to precharge command interval (same bank) (bl = 4 (to stop write operation)) w[x p*z p*3 p*k w g "% "Cg*[[ p*8 g] g[ write to precharge command interval (same bank) (bl = 4 (to write all data))
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 40 bank active command interval 1. same bank: the interval between the two bank active commands must be no less than trc. 2. in the case of different bank active commands: the interval between the two bank active commands must be no less than trrd. w[x w * f fpz p* *w "; *w "; fpz p* "w bank active to bank active for same bank w[x w * f fpz p* fp8 p* *w ";qz *w ";q3 ""g bank active to bank active for different bank mode register set to bank active command interval the interval between setting the mode register and executing a bank active command must be no less than lmrd. w[x w * ] "p f * ]" %]"g *w fpwp"; ;w;gC mode register set to bank active command interval
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 41 dqm control the dqm mask the dq data. the udqm and ldqm mask the upper and lower bytes of the dq data, respectively. the timing of udqm/ldqm is different during reading and writing. reading when data is read, the output buffer can be controlled by dqm. by setting dqm to low, the output buffer becomes low-z, enabling data output. by setting dqm to high, the output buffer becomes high-z, and the corresponding data is not output. however, internal reading operations continue. the latency of dqm during reading is 2 clocks. writing input data can be masked by dqm. by setting dqm to low, data can be written. in addition, when dqm is set to high, the corresponding data is not written, and the previous data is held. the latency of dqm during writing is 0 clock. w[x g pz p3 g;gpvpkp[ p8 g] a reading w[x g pz p3 g%gpvpzp[ p8 g] writing
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 42 refresh auto-refresh all the banks must be precharged before executing an auto-refresh command. since the auto-refresh command updates the internal counter every time it is executed and determines the banks and the row addresses to be refreshed, external address specification is not required. the refresh cycles are required to refresh all the row addresses within tref (max.). the output buffer becomes high-z after auto-refresh start. in addition, since a precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by the precharge command is not required. self-refresh after executing a self-refresh command, the self-refresh operation continues while cke is held low. during self- refresh operation, all row addresses are refreshed by the internal refresh timer. a self-refresh is terminated by a self-refresh exit command. before and after self-refresh mode, execute auto-refresh to all refresh addresses in or within tref (max.) period on the condition 1 and 2 below. 1. enter self-refresh mode within time as below* after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. 2. start burst refresh or distributed refresh at equal interval to all refresh addresses within time as below*after exiting from self-refresh mode. note: tref (max.) / refresh cycles. others power-down mode the sdram enters power-down mode when cke goes low in the idle state. in power down mode, power consumption is suppressed by deactivating the input initial circuit. power down mode continues while cke is held low. in addition, by setting cke to high, the sdram exits from the power down mode, and command input is enabled from the next clock. in this mode, internal refresh is not performed. clock suspend mode by driving cke to low during a bank active or read/write operation, the sdram enters clock suspend mode. during clock suspend mode, external input signals are ignored and the internal state is maintained. when cke is driven high, the sdram terminates clock suspend mode, and command input is enabled from the next clock. for details, refer to the "cke truth table".
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 43 timing waveforms read cycle uf. w uf. uf. - -: v- w -z vw v-w v: u wy. w z zfoi zfoi - - w- w- - w- - v-wff[f= uff[f+ uf.f fffffff[fff w-
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 44 write cycle - -: v- w -z vw v-w v: u wy. w zfoi zfoi - - - - z uf. uf. w uf. -f[f= uf[f+ uf.f fffffff[fff z mode register set cycle . y = 7 + v q q y. yy y= y7 y+ yv yq y y yq - -: v- vw v-w v: u w z zfoi zfoi x n7 ? b ? +1 b ? +2 b ? +3 lmrd valid c: b ? code lrcd lrp precharge if needed mode register set bank 3 active bank 3 read r: b c: b output mask vil l rcd = 3 /cas latency = 3 burst length = 4 = vih or vil
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 45 read cycle/write cycle . y = 7 + v q q y.yyy=y7y+yvyqyyyq=. l -l l -l -l, -lu ny n= n7 ny n= n7 , ,ny u uny un= un7 -: vw v- v-w v: w z zfoi zfoi - u l -l l -l -l, -lu ny n= n7 ny n= n7 , ,ny u uny un= un7 uf. w uf. uf7 w uf7 uf7 uf7 uf. uf7 uf. w uf. uf7 w uf7 uf7 uf7 uf. uf7 -: vw v- v-w v: w z zfoi zfoi u x x f vwxv-wff[f7 v-wff[f7 uff[f+ fffffff[f ff f vwxv-wff[f7 v-wff[f7 uff[f+ fffffff[fff read/single write cycle . y = 7 + v q q y. yy y= y7 y+ yv yq y y yq =. l -l l -l, l -l -l uf. w uf. uf7 w uf. uf. uf7 uf. w uf. uf. uf. l uf7 w -l uf. ny n= n7 uf. uf. -: vw v- v-w v: w z zfoi zfoi - u -: vw v- v-w v: w z u -l ny n7 ny n= n7 -l vf vwxv-wff[f7 v-wff[f7 uff[f+ fffffff[f ff zfoi zfoi
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 46 read/burst write cycle . y = 7 + v q q y. yy y= y7 y+ yv yq y y yq =. l -l l -l, l -l -l ny n= n7 ny ny n= n7 uf. w uf. uf. uf. l uf7 w -: vw v- v-w v: w z - u -: vw v- v-w v: w z u ny n= n7 n7 uf. w uf. uf7 w - uf. uf. uf7 vuf vwxv-wff[f7 v-wff[f7 uff[f+ fffffff[f ff zfoi zfoi zfoi zfoi auto refresh cycle . y = 7 + v q q y. yy y= y7 y+ yv yq y y yq =. - -: v- v-w v: u w z zfoi zfoi x f wf w uf. - - wf uf. l -l wy.[y vw ny ff f vwxv-wff[f= v-wff[f= uff[f+ fffffff[fff
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 47 self refresh cycle - -: v- vw v-w v: u w z zfoi zfoi f f ff w ff f fff -:f wy.[y - ff vwxv-wff[f7 -f[f7 uf[f+ fffffff[f ff x - : ff f clock suspend mode .y=7 + v q q y.yyy=y7y+yvyqyyyq=. l -l l ny n= n7 ny n= l -l l -l ny n= ny n= n7 -l u. w wf f wf f u. u7 w f f u. u7 :fu7 u. u. w wf f wf f u7 w f f u7 u. :fu7 n7 -: vw v- v-w v: w z - u -: vw v- v-w v: w z u n7 x x f vwxv-wff[f= v-wff[f= uff[f+ fffffff[fff f vwxv-wff[f= v-wff[f= uff[f+ fffffff[fff zfoi zfoi zfoi zfoi
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 48 power down mode - -: v- vw v-w v: u w z zfoi zfoi f f ff wfuf. ff f -:f lf wy.[y x ff vwxv-wff[f7 v-wff[f7 uff[f+ fffffff[fff initialization sequence qy. v= v7 v+ + +q v. vy wf uf f - - wf . y=7+vq - -: v- vw v-w v: w z z z wf f vv x
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 49 package drawing lf :-wx=x..yqx.y .hyq w w u u .hy. .h. y.hyq v+ = y= ==h==ff.hy. yh.f ?
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 50 recommended soldering conditions please consult with our sales offices for soldering conditions of the eds51xxabta. type of surface mount device eds51xxabta: 54-pin plastic tsop (ii)
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 51 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
eds5104abta, eds5108abta, eds5116abta preliminary data sheet e0250e10 (ver. 1.0) 52 ]z3Cz3z- ypppppppppppppppppppp pppCp]4p%b Cp]4p%bppppppppppppp ,ppppp4p4ppppippCp]4p%bpp ppppppppppppppppbpyp4p 4ppp4ppppp4pppppp ppCp]4p%bppb gpp4pppppppppppp ppppppppbpppp p4pppppppppypppppp pppppbpCp]4p%bppppppp pppppppppppp4pppb [product applications] elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] this product is not designed to be resistant to electromagnetic waves or radiation. this product must be used in a non-condensing environment. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

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